In many modern circuit applications, it is desirable to increase the speed of operation of the circuit application. For example, in microprocessor design the circuits which make up speed-limiting portions or affect the speed of the microprocessor are constantly scrutinized and re-designed to increase the overall microprocessor speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated processing capabilities in a shorter amount of time. It is known in the CMOS manufacturing art to target the threshold voltage of transistors given certain circuit expectations. Particularly, typically a manufacturer will build transistors, or make available transistor fabrication processes, which include transistors of a given threshold voltage. When providing this process, the manufacturer typically considers the tradeoff in speed improvement versus power consumption. To increase operational speed, it is known that the threshold voltage of all of the transistors within a circuit may be reduced. By reducing the threshold voltage, the drive current of these transistors is increased. However, the leakage current of those same transistors is also increased. This approach becomes even more limiting as power supply voltages are reduced and the threshold voltage of the transistor becomes a greater percentage of the power supply voltage. Consequently, one approach is to lower the threshold voltage of the transistor but this increases current leakage and therefore also increases overall standby power consumption. Thus, often a manufacturer anticipates a certain level of leakage to be the acceptable limit, and in view of that limit, adjusts known parameters so that each of the transistors of the circuit share a designated threshold voltage which will provide that limit.
As MOSFET process technology continues to scale to smaller transistors, both gate length and gate oxide thickness decrease. This mandates a supply voltage (V.sub.dd) reduction to maintain MOSFET gate integrity. Although power dissipation is decreasing favorably according to V.sub.dd.sup.2 due to scaling, the propagation delay degrades proportional to (V.sub.dd -V.sub.t). Thus, to both enhance performance and reduce power dissipation, multiple-threshold-voltage MOSFETs are crucial for deep sub-micron CMOS processes, especially when V.sub.dd is in the one volt range. However, the LVT MOSFET must be applied to the circuit architecture judiciously to maintain proper noise immunity and to prevent excessive subthreshold leakage power dissipation which is detrimental to any power management techniques of an energy-sensitive microprocessor design.
While the above approaches are representative of the art for advancing circuit operational speed, they provide various limitations or drawbacks. For example, the logic speed is still limited by the threshold voltage of the transistors used in the logic. As another example, and as mentioned above, an advance in speed by reducing threshold voltage necessarily increases standby power consumption caused by leakage current. This invention provides increased circuit speed while reducing leakage current as compared to the current state of the art.